Collaboration spans interface and memory IP utilizing 2nm gate-all-around BSPDN technology and AI-driven reference flows.
SAN JOSE, CA, Dec 12, 2014 – Cadence Design Systems, Inc. announced it is collaborating with Rapidus Corporation to provide co-optimized AI-driven reference design flows and a broad IP portfolio to support the Rapidus 2nm gate-all-around (GAA) process and leverage the design and manufacturing benefits from Rapidus’ backside power delivery network (BSPDN) technology. As the semiconductor industry struggles to keep up with significantly increasing design challenges driven by the need for more computation, GAA and BSPDN manufacturing technologies are becoming vital to meet increasingly stringent power, performance and area requirements.
The AI-driven digital and analog/mixed signal reference design flows encompass numerous solutions from Cadence, including Cadence Cerebrus Intelligent Chip Explorer, Cadence JedAI Solution, Genus Synthesis Solution, Conformal, Joules RTL Power Solution, Innovus Implementation System, Tempus Timing Signoff Solution, Quantus Extraction Solution, Voltus IC Power Integrity Solution, Virtuoso Studio, Spectre X Simulator, Voltus-XFi Custom Power Integrity Solution, and Pegasus Verification System. Customers will be able to use a broad portfolio of Cadence interface and memory IP components, including HBM4, 224G SerDes, and PCI Express (PCIe) 7.0.
“Our collaboration with Cadence on 2nm BSPDN technology puts us at the industry’s forefront, marking a major leap in semiconductor innovation for performance and efficiency. By combining our expertise, we’re excited to set new technology standards and create transformative solutions for our mutual customers and the industry,” said Dr. Atsuyoshi Koike, CEO of Rapidus.
“Our broad collaboration with Rapidus for 2nm GAA BSPDN technology leverages Cadence’s AI-driven solutions to solve real-world problems and meet customer needs,” said Dr. Anirudh Devgan, president and CEO at Cadence. “By bringing together Cadence’s advanced interface and memory IP technology, reference flows and Rapidus’ process technology, we’re empowering the buildout of the AI infrastructure of tomorrow.”
For more information, visit cadence.com.
